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PRELIMINARY
CY14B101L
1-Mbit (128K x 8) nvSRAM
Features
* 25 ns, 35 ns, and 45 ns access times * "Hands-off" automatic STORE on power down with only a small capacitor * STORE to QuantumTrapTM nonvolatile elements is initiated by software, device pin, or AutostoreTM on power down * RECALL to SRAM initiated by software or power up * Infinite READ, WRITE, and RECALL cycles * 10 mA typical ICC at 200 ns cycle time * 200,000 STORE cycles to quantum trap * 20-year data retention @ 55C * Single 3V operation +20%, -10% * Commercial and industrial temperature * SOIC and SSOP packages * RoHS compliance
Functional Description
The Cypress CY14B101L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing, the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles; while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
Logic Block Diagram
QuantumTrap 1024 x 1024
A5 A6 A7 A8 A9 A 12 A 13 A 14 A 15 A 16
V CC
V CAP
STORE
POWER CONTROL STORE/ RECALL CONTROL
ROW DECODER
STATIC RAM ARRAY 1024 X 1024
RECALL
HSB
SOFTWARE DETECT COLUMN IO
A15
- A0
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
INPUT BUFFERS
DQ 1
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10 A 11
OE
CE WE
Cypress Semiconductor Corporation Document #: 001-06400 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 24, 2007
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PRELIMINARY
Pin Configurations
CY14B101L
V CAP A 16 A 14 A 12 A7 A6 A5 NC A4 NC NC NC V SS NC NC DQ0 A3 A2 A1 A0 DQ1 DQ2 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40
V CC A 15 HSB WE A 13 A8 A9 NC A 11 NC NC NC V SS NC NC DQ 6 OE A 10 CE DQ7 DQ5 DQ4 DQ3 V CC
48-SSOP
Top View
(Not To Scale)
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
V CAP A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
V CC A 15 HSB WE A 13 A8 A9 A 11 OE A 10 CE DQ7 DQ6 DQ5 DQ4 DQ3
32-SOIC
Top View
(Not To Scale)
26 25 24 23 22 21 20 19 18 17
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PRELIMINARY
Pin Definitions
Pin Name A0 - A16 WE CE OE VSS VCC HSB IO Type Input Description Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
CY14B101L
DQ0 - DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. Input Input Input Ground Write Enable Input, Active LOW. When selected LOW, enables data on the IO pins to be written to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. IO pins are tri-stated on deasserting OE high. Ground For The Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs To The Device. Input Output Hardware Store Busy (HSB). When low this output indicates a hardware store is in progress. When pulled low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected. (connection optional) Power Supply Autostore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connect. Do not connect this pin to the die. The data on the common IO pins IO0-7 will be written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep the OE high during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left low, internal circuitry turns off the output buffers tHZWE after WE goes low.
VCAP NC
Device Operation
The CY14B101L nvSRAM is made up of two functional components paired in the same physical cell, the SRAM memory cell and the nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Transfer of data can be from the SRAM to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The CY14B101L supports infinite reads and writes just like a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200,000 STORE operations.
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of the three storage operations. These three operations are Hardware Store activated by HSB, Software Store activated by an address sequence, and AutoStore on device power down. AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101L. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 1 on page 4 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC Characteristics table for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up must be placed on WE to hold it inactive during power up. To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress.
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE are low while WE and HSB are high. The address specified on pins A0-16 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. It remains valid until another address change, or until CE or OE is brought high, or WE or HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle.
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PRELIMINARY
Figure 1. AutoStore Mode
CY14B101L
a RECALL cycle will automatically be initiated and takes tHRECALL to complete.
V CC
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B101L software STORE cycle is initiated by executing sequential CE-controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence will be aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled READs or OE controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle commences and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that OE be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
V CAP
V CAP
V CC
10k Ohm
WE
Hardware STORE Operation
The CY14B101L provides the HSB pin for controlling and acknowledging the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven low, the CY14B101L conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY14B101L continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the CY14B101L continues to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY14B101L remains disabled until the HSB pin returns high. Leave the HSB unconnected if is not used.
0.1UF
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH,
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PRELIMINARY
Table 1. Mode Selection CE H L L L WE X H L H OE X L X L A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall IO
CY14B101L
Power Standby Active Active Active[1, 2, 3]
Output High-Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High-Z Output Data Output Data Output Data Output Data Output Data Output High-Z
L
H
L
Active[1, 2, 3]
L
H
L
Active ICC2[1, 2, 3]
L
H
L
Active[1, 2, 3]
Notes 1. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes. 3. IO state depends on the state of OE. The IO table shown is based on OE Low.
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PRELIMINARY
Preventing AutoStore
Disable the AutoStore function by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of CE-controlled READ operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8B45 AutoStore Disable Re-enable the AutoStore by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of CE-controlled READ operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
CY14B101L
connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduces circuit noise.
Low Average Active Power
CMOS technology provides the CY14B101L the benefit of drawing less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ/WRITE cycle time. Worst case current consumption is shown for commercial temperature range VCC = 3.6V and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101L depends on the following items: 1. The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. The operating temperature. 5. The VCC level. 6. IO loading. Figure 2. Current vs. Cycle Time
Data Protection
The CY14B101L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B101L is in a WRITE mode (CE and WE low) at power up after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brownout conditions.
Noise Considerations
The CY14B101L is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 F
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PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may shorten the device battery life. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND ......... -0.5V to 4.1V Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Input Voltage ..........................................-0.5V to VCC + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VCC + 2.0V
CY14B101L
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Lead Soldering Temperature (three seconds) .................................... +260C Output Short Circuit Current [4] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (in accordance with MIL-STD-883, method 3015) Latch up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) [5, 6, 7] Parameter ICC1 Description Average VCC Current Test Conditions tRC = 25 ns tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. All inputs do not care, VCC = Max Average current for duration tSTORE Commercial Min Max 65 55 50 55 (tRC = 45 ns) 6 10 Unit mA mA mA mA mA mA
Industrial
ICC2 ICC3
Average VCC Current during STORE
Average VCC Current at WE > (VCC - 0.2). All other inputs cycling. tAA = 200 ns, 3V, 25C Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. typical Average VCAP Current All inputs do not care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current WE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -1 -1 2.0 Vss - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V rated 17 2.4
ICC4 ISB
3 3
mA mA
IIX IOZ VIH VIL VOH VOL VCAP
Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output VCC = Max, VSS < VIN < VCC, CE or OE > VIH Leakage Current Input HIGH Voltage [7] Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
+1 +1 Vcc + 0.3 0.8 0.4 120
A A V V V V F
Notes 4. Outputs shorted for no more than one second. No more than one output shorted at a time. 5. Typical conditions for the active current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 3V. Not 100% tested. 6. The HSB pin has IOUT = -10 A for VOH of 2.4 V, this parameter is characterized but not tested. 7. VIH changes by 100 mV when VCC > 3.5V.
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PRELIMINARY
Capacitance [7]
Parameter CIN COUT Parameter Description Input Capacitance Output Capacitance
[7]
CY14B101L
Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V
Max 7 7
Unit pF pF
Thermal Resistance
Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case)
Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
32-SOIC 48-SSOP TBD TBD TBD TBD
Unit C/W C/W
JA JC
AC Test Loads
R1 577 3.0V OUTPUT 30 pF R2 789 3.0V OUTPUT 5 pF R2 789 R1 577
FOR TRI-STATE SPECS
AC Test Conditions
Input Pulse Levels.................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)...................... < 5 ns Input and Output Timing Reference Levels................... 1.5 V
Note 8. These parameters are guaranteed but not tested.
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PRELIMINARY
AC Switching Characteristics
Parameter Cypress Parameter Alt. Parameter Description 25 ns part Min Max 35 ns part Min Max
CY14B101L
45 ns part Min Max Unit
SRAM Read Cycle tACE tRC [9] tAA
[10]
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tOW
[11] [11]
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 0 3 3 25
25 35 25 12 3 3 10 0 10 0 25
35 45 35 15 3 3 13 0 13 0 35
45
ns ns
45 20
ns ns ns ns
tDOE tOHA tLZCE [11] tHZCE tLZOE tPU [7] tPD
[7]
15
ns ns
tHZOE [11]
15
ns ns
45
ns
SRAM Write Cycle tWC tPWE tSCE tSD tHD tAW tSA tHA tLZWE [11] Write Cycle Time Write Pulse Width Chip Enable to End of Write Data SetUp to End of Write Data Hold After End of Write Address SetUp to End of Write Address SetUp to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write 3 25 20 20 10 0 20 0 0 10 3 35 25 25 12 0 25 0 0 13 3 45 30 30 15 0 30 0 0 15 ns ns ns ns ns ns ns ns ns ns
tHZWE [11, 12] tWZ
Notes 9. WE must be HIGH during SRAM read cycles. 10. Device is continuously selected with CE and OE low. 11. Measured 200 mV from steady state output voltage. 12. If WE is low when CE goes low, the outputs remain in the high impedance state.
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PRELIMINARY
AutoStore/Power Up RECALL
Parameter tHRECALL [13] tSTORE [14, 15] VSWITCH tVCCRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 CY14B101L Min Max 20 12.5 2.65
CY14B101L
Unit ms ms V s
Software Controlled STORE/RECALL Cycle [16, 17, 18]
Parameter tRC tAS tCW tGHAX tRECALL tSS
[19, 20]
Description STORE/RECALL Initiation Cycle Time Address SetUp Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time
25 ns part Min 25 0 20 1 50 70 Max
35 ns part Min 35 0 25 1 50 70 Max
45 ns part Min 45 0 30 1 50 70 Max
Unit ns ns ns ns s s
Hardware STORE Cycle
Parameter tDELAY [21] tHLHX Description Time allowed to complete SRAM Cycle Hardware STORE Pulse Width CY14B101L Min 1 15 Max 70 Unit s ns
Notes 13. tHRECALL starts from the time VCC rises above VSWITCH. 14. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place. 15. Industrial grade devices require 15 ms max. 16. The software sequence is clocked with CE controlled or OE controlled READs. 17. The six consecutive addresses must be read in the order listed in the Table 1, "Mode Selection," on page 5. WE must be HIGH during all six consecutive cycles. 18. A 600 resistor must be connected to HSB to use the software command. 19. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register the command. 20. Commands like STORE and RECALL lock out IO until operation is complete, which further increases this time. See the specific command. 21. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
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PRELIMINARY
Switching Waveforms
SRAM Read Cycle 1(address controlled) [9, 10, 22]
CY14B101L
tRC
ADDRESS
t AA t OHA
DQ (DATA OUT) DATA VALID
SRAM Read Cycle 2 (CE and OE controlled) [9, 22]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
DQ (DATA OUT)
tLZOE t PU
tDOE
DATA VALID
tHZOE
ACTIVE
ICC
STANDBY
Note 22. HSB must remain HIGH during READ and WRITE cycles.
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PRELIMINARY
Switching Waveforms (continued)
SRAM Write Cycle 1(WE controlled) [22, 23]
CY14B101L
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
SRAM Write Cycle 2 (CE controlled)
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Note 23. CE or WE must be > VIH during address transitions.
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PRELIMINARY
Switching Waveforms (continued)
Figure 3. AutoStore/Power Up RECALL
CY14B101L
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Figure 4. CE-Controlled Software STORE/RECALL Cycle [17]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
tGLAX tGHAX
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
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PRELIMINARY
Switching Waveforms (continued)
Figure 5. OE-Controlled Software STORE/RECALL Cycle [17]
CY14B101L
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tSA
OE
tSCE
tGHAX tGLAX
DQ (DATA)
DATA VALID
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Figure 6. Hardware STORE Cycle
HSB (IN)
tHLHX tSTORE
HIGH IMPEDANCE
HSB (OUT)
tHLBL
HIGH IMPEDANCE
t DELAY
DQ (DATA OUT) DATA VALID DATA VALID
Figure 7. Soft Sequence Processing [19, 20]
Soft Sequence Command
ADDRESS
ADDRESS # 1 ADDRESS # 6
34 t SS
Soft Sequence Command
ADDRESS # 1 ADDRESS # 6
34 t SS
VCC
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PRELIMINARY
CY14B101L
PART NUMBERING NOMENCLATURE CY 14 B 101 L - SZ 25 X C T
Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Data Bus: L - x8 Density: 101 - 1 Mb
Pb-Free Package: SZ - 32 SOIC SP - 48 SSOP
Voltage: B - 3.0V
NVSRAM 14 - AutoStore + Software Store + Hardware Store
Cypress
Ordering Information
All of the following mentioned parts are of "Pb-free" type. Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts. Speed (ns) 25 35 45 45 Ordering Code CY14B101L-SZ25XCT CY14B101L-SP25XCT CY14B101L-SZ35XCT CY14B101L-SP35XCT CY14B101L-SZ45XCT CY14B101L-SP45XCT CY14B101L-SZ45XIT CY14B101L-SP45XIT CY14B101L-SZ45XI CY14B101L-SP45XI Package Diagram 51-85127 51-85061 51-85127 51-85061 51-85127 51-85061 51-85127 51-85061 51-85127 51-85061 32-pin SOIC 48-pin SSOP 32-pin SOIC 48-pin SSOP 32-pin SOIC 48-pin SSOP 32-pin SOIC 48-pin SSOP 32-pin SOIC 48-pin SSOP Industrial Commercial Commercial Package Type Operating Range Commercial
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PRELIMINARY
Package Diagrams
Figure 8. 32-pin (300-Mil) SOIC, 51-85127
PIN 1 ID
16 1
CY14B101L
0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642]
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119
MIN. MAX.
17
32
PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG.
SEATING PLANE
0.810[20.574] 0.822[20.878]
0.090[2.286] 0.100[2.540]
0.004[0.101] 0.050[1.270] TYP. 0.014[0.355] 0.020[0.508] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] 0.021[0.533] 0.041[1.041] 0.006[0.152] 0.012[0.304]
51-85127-*A
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PRELIMINARY
Package Diagrams (continued)
Figure 9. 48-Pin Shrunk Small Outline Package, 51-85061
CY14B101L
51-85061-*C
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06400 Rev. *E
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY14B101L 1-Mbit (128K x 8) nvSRAM Document Number: 001-06400 REV. ** *A *B ECN NO. 425138 437321 471966 Issue Date See ECN See ECN See ECN Orig. of Change TUP TUP TUP New Data Sheet Show Data Sheet on External Web Description of Change
CY14B101L
Changed ICC3 from 5 mA to 10 mA Changed ISB from 2 mA to 3 mA Changed VIH(min) from 2.2V to 2.0V Changed tRECALL from 40 s to 50 s Changed Endurance from 1 Million Cycles to 500K Cycles Changed Data Retention from 100 Years to 20 Years Added Soft Sequence Processing Time Waveform Updated Part Numbering Nomenclature and Ordering Information Changed from Advance to Preliminary Changed the term "Unlimited" to "Infinite" Changed Endurance from 500K Cycles to 200K Cycles Added temperature spec to Data Retention - 20 years at 55C Removed Icc1 values from the DC table for 25 ns and 35 ns industrial grade Changed Icc2 value from 3 mA to 6 mA in the DC table Added a footnote on VIH Changed VSWITCH(min) from 2.55V to 2.45V Added footnote 17 related to using the software command Updated Part Nomenclature Table and Ordering Information Table Removed VSWITCH(min) spec from the AutoStore/Power Up RECALL table Changed tGLAX spec from 20 ns to 1 ns Added tDELAY(max) spec of 70 s in the hardware STORE cycle table Removed tHLBL specification Changed tSS specification form 70 s (min) to 70 s (max) Changed VCAP(max) from 57 F to 120 F Added footnote related to HSB Changed tGLAX to tGHAX
*C
503272
See ECN
PCI
*D
597002
See ECN
TUP
*E
688776
See ECN
VKN
Document #: 001-06400 Rev. *E
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